1. Field of the Invention
This invention relates to the fabrication of integrated circuit (IC) devices, and more particularly to a new method of fabricating dynamic random access memory (DRAM) cell capacitor which has multi-layered stacked electrode plate configuration which improves its capacitance. This invention also relates to the configuration of this new capacitor.
2. Description of the Prior Art
Dynamic random access memory (DRAM), which comprises an array of memory cells, is a widely utilized integrated circuit (IC) device. Each memory cell in the array comprises, as shown in FIG. 1, a metal-oxide semiconductor field-effect transistor (MOSFET) 10 and a capacitor 12. The gate terminal of the MOSFET 10 is connected to a word line (WL), and the other two terminals (source and drain) of the MOSFET 10 are connected to the capacitor 12 and a bit line (BL), respectively. When reading the contents of the memory cell, the gate terminal receives a pulse on the word line WL to turn-on the MOSFET 10. The capacitor 12 is then discharged and the bit of data stored therein is sent out the bit line (BL). On the other hand, when writing data to the memory cell, data is provided on the bit line and the gate terminal receives a pulse through the word line to turn-on the MOSFET 10. The capacitor 12 is then charged to store the data on the bit line.
As is well known to persons skilled in this art, a capacitor is utilized for the storage of the data content of each memory cell. The bit in question, either a one or a zero, as stored in the memory cell, is determined by whether or not the capacitor is charged or discharged. Due to the inherent nature of the DRAM design, the capacitor should possess high capacitance in order to maintain its data content for as long a period of time as possible.
A stacked capacitor is a commonly used structure in DRAM cells. Referring to FIG. 2, there is shown a silicon substrate 2. Field oxide 20, gate electrode 32, and source/drain areas 30 are formed on the silicon substrate 2 successfully. A silicon dioxide layer 24 is deposited over the gate electrode 32 and source/drain areas 20, wherein a contact opening is formed therein to expose the desired source/drain areas 30. A first polysilicon layer 34 (bottom electrode plate of the stacked capacitor), a dielectric layer 36, such as nitride/oxide (NO) or oxide/nitride/oxide (ONO) layers, and a second polysilicon layer 38 (top electrode plate of the stacked capacitor) are next formed on the silicon dioxide layer 24, respectively, so as to cnstruct a cell capacitor. The first polysilicon layer 34 is connected to the desired source/drain areas 30 through the contact opening within the silicon dioxide layer 24.
With the continuous increase of device density on integrated circuits, the DRAM cell area is getting smaller which results in a smaller capacitor and hence less capacitance. There are two methods to increase the capacitance: (i) decrease the effective dielectric thickness and (ii) increase the capacitor's surface area. However, higher capacitance values cannot be obtained without seriously degrading the device retention time because dielectric films thinner than 50 .ANG. presently have excessive leakage currents due to direct carrier tunneling. For a given capacitor dielectric film, the larger the surface area of the storage electrodes, the higher the capacitance. Using trenched capacitors for DRAM cells is another scheme for increasing capacitance. The trenched capacitor is formed within a trench nearby a transistor device. This kind of capacitor suffers from a reduced etch rate for high-aspect-ratio trenches, and thus the processing is time consuming and hence expensive. Also, inevitable crystalline defects occur by this process.